The present invention relates to an electrically erasable programmable nonvolatile semiconductor storage (flash EEPROM).
A flash EEPROM has a memory cell transistor having a stack structure, in which data is written by channel hot electrons and erased by Fowler-Nordheim tunnel current. This type of memory requires an X (row) decoder for selecting a word line when writing or erasing data. However, data erasing for a conventional flash EEPROM is considered by assuming batch erasing of all bits and therefore, it cannot correspond to block erasing in a minute unit. Therefore, a memory realizing block erasing in a minute unit is proposed (official gazette of Japanese Patent Laid-Open No. 6-215591).
FIG. 5A is a block diagram of the flash EEPROM disclosed in the official gazette of Japanese Patent Laid-Open No. 6-215591) and FIG. 5B is a block diagram of the X decoder of the flash EEPROM.
The flash EEPROM comprises a memory cell array 41 in which memory cell transistors M00 to M11 are arranged like a matrix, word lines W0 and W1 connected to the control gate of the memory cell transistor of each row in common, bit lines B0 and B1 connected to the drain of the memory cell transistor of each column in common, an X decoder 42 for selecting a predetermined word line in accordance with an X address supplied from an external unit, and a Y decoder 43 for selecting a predetermined bit line in accordance with a Y address supplied from an external unit.
The X decoder 42 comprises a predecoder circuit (not shown), a NAND gate G41, an inverter gate IV41 for inverting an output signal of the NAND gate G41, and two transfer gates T1 and T2 respectively provided for each word line. Moreover, the transfer gate T1 comprises an N-channel MOS transistor Q41 and a P-channel MOS transistor Q42 and the transfer gate T2 comprises an N-channel MOS transistor Q43 and a P-channel MOS transistor Q44. Moreover, the NAND gate G41 and inverter gate IV41 are provided every predetermined number of word lines.
In outputs A0 and A1 of the predecoder circuit, a positive voltage (5 V for data read or 12 V for data write) is output from an output corresponding to a selected word line when data is read or written and -10 V is output when data is erased. Moreover, 0 V is output from an output corresponding to a nonselected word line when data is read or written and 3 V is output when data is erased.
Moreover, a voltage VWL supplied to the sources of the transistors Q43 and Q44 from a power supply (not shown) becomes 3 V when data is erased and becomes 0 V except the time when data is erased.
In the case of the above memory, because an "H"-level signal is input to every NAND gate G41 of a block including a selected word line, the output signal of the inverter gate IV41 of the block becomes "H"-level. Thereby, T1 of the transfer gates T1 and T2 is turned on.
Moreover, because an "L"-level signal is input to every NAND gate G41 of a block including a nonselected word line, the output signal of the inverter gate IV41 of the block becomes "L"-level. Thereby, T2 of the transfer gates T1 and T2 is turned on.
Thus, when data is read or written, a positive voltage (5 V for data read or 12 V for data write) supplied from the predecoder circuit is output to the selected word line through the transfer gate T1 and 0 V supplied from the predecoder circuit or an internal power supply is output to the nonselected word line through the transfer gate T1 or T2.
Moreover, when data is erased, -10 V supplied from the predecoder circuit is output to the selected word line through the transfer gate T1 and 3 V supplied from the predecoder circuit or the internal power supply is output to the nonselected word line through the transfer gate T1 or T2. Thus, it is possible to erase data in blocks including a plurality of word lines.
A voltage of 3 V is supplied to the nonselected word line when data is erased in order to apply a voltage higher than 0 V to the control gate of a nonselected memory cell transistor and decrease the potential difference between a source and a gate so that erroneous erasing (drain disturbing phenomenon) does not occur in the nonselected memory cell.